This application note describes the setup within the Xilinx FPGA tools to be able to establish a high-bandwidth interface between an IBM Power Processor and the latest Xilinx FPGAs via an interface implementation from Rambus Inc. It has been currently successfully evaluated and tested on a system prototyping platform up to a data rate of 3Gbit/sec per lane and can be expanded to multiple bytes. It represents one of the fastest coherent/non-coherent processor to FPGA interfaces available in the industry.
By: Ibrahim Ouda; Kai Schleupen
Published in: RC24596 in 2008
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