Sequential Lateral Solidification of Silicon Thin Films on Low-k Dielectrics for Low Temperature Integration

We present the excimer laser crystallization of amorphous silicon on a low dielectric constant (low-k) insulator for VLSI monolithic 3D integration and demonstrate that low dielectric constant materials are suitable substrates for 3D integration through laser crystallization of silicon thin lms. We crystallized 100 nm amorphous silicon on top of SiO₂ and SiCOH (low-k) dielectrics, at different material thicknesses (1mu m, 0.75 mu m and 0.5 m). The amorphous silicon crystallization on low-k material requires 35% less laser energy than on an SiO₂ dielectric. This difference is related to the the thermal conductivity of the two materials, in agreement with one dimensional simulations of the crystallization process. We analyzed the morphology of the material through defect-enhanced microscopy, Raman, and X-ray diffraction analysis. SEM micrographs show that polycrystalline silicon is characterized by micron-long grains with an average width of 543 nm for the SiO₂ sample and 570 nm for the low-k samples. Comparison of the Raman spectra does not show any major difference in film quality for the two different dielectrics, and polycrystalline silicon peaks are closely placed around 517 cm^-1. From X-ray diffraction analysis, the material crystallized on SiO₂ shows a preferential (1,1,1) crystal orientation. In the SiCOH case the (1,1,1) peak strength decreases dramatically and samples do not show preferential crystal orientation. A 1D fiite element method simulation of the crystallization process on a back end of line structure, shows that interconnect lines experience a maximum temperature lower than 70 C also for the 0.5 mu m dielectric, which is a favorable condition for monolithic 3D integration.