A new design approach is presented for FETs at their limit of scaling where the power-performance trade-off is achieved by intentional channel length variation. The method was applied via simulation to double gate and thin SOI FETs and it was shown that a single, midgap metal was able to handle the entire power-performance range in an almost optimal manner, obviating the need for multiple work-function gates. For bulk N-FETs a single work function of ~0.1V below midgap was near optimal.
By: Paul M. Solomon, Ihsan Djomehri
Published in: RC22379 in 2002
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