Charge Trapping in SiO2/HfO2 Dual Layer Gate Stacks

Charge trapping in SiO2/HfO2 dual layer gate stacks with poly-Si electrodes is reviewed. Results obtained with different measurement techniques are compared and it is shown that pulsed measurement techniques, such as charge pumping (using amplitude sweeps) and the pulsed
Id-Vg technique, are useful to quantify the fast transient charging effects in these gate stacks. A trapping model is proposed to explain the observed transient charging behavior.

By: E. Cartier, A. Kerber, L. Pantisano

Published in: RC23080 in 2004

LIMITED DISTRIBUTION NOTICE:

This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.

rc23080.pdf

Questions about this service can be mailed to reports@us.ibm.com .