AQUAIA: A CAD Tool for On-Chip Interconnect Modeling, Analysis, and Optimization

The development of CAD tools for the modeling, analysis, and
optimization of on-chip interconnect structures presents many
challenges not found in the context of electronic package design and
analysis. In this paper, we summarize these challenges and report on a
new tool called AQUAIA that addresses them based on the physics
of electrical parameter modeling of on-chip interconnects. Specifically, we show how the complexities of on-chip interconnect modeling and analysis can be contained using predefined, representative, three-dimensional signal and power interconnect templates fully compatible with the metal/dielectric
back-end-of-the-line (BEOL) stack. These templates enable the fast modeling and simulation of delay, rise/fall time, and crosstalk of signal nets that fully account for the emerging problems of on-chip wiring, including inductive effects and broadband frequency dependence.  We also give examples of how to use AQUAIA for interconnect design verification, wiring rule generation, and BEOL process integration.