Delay and Throughput Performance of Speeded-Up Input-Queueing Packet Switches

In this note, we study the performance of high-speed packet switches
that employ a combination of input queueing and output queueing.
Specifically, we consider switches whose fabric runs at a speed
greater than that of the input and output links. The purpose of this
note is to highlight the result that a speedup factor of less than two
for the switch fabric over the input link speed is sufficient to
achieve full input link utilization ($100$\% throughput) for many
switch architectures. This result seems to have been overlooked by
most researchers to date, who have often assumed that a speedup factor
equal to the number of switch input ports $n$ is necessary in order to
achieve full link utilization. Consequently, we precisely specify the
conditions under which a speedup factor of less than two is adequate.
Furthermore, we also present simulation results on delay performance
which show that a speedup factor of two is again sufficient to achieve
nearly the same delay performance as that of an output queueing
switch, even for bursty traffic. Finally, we consider the performance
of switches with memory inside the switch fabric and see that such
switches require even less speedup in order to achieve full link
utilization.