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The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105mW at a supply voltage of 0.7V, corresponding to an energy efficiency of 4.1 pJ/b. A data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b at a supply voltage of 0.8V. The VD, implemented in an experimental chip fabricated in 14-nm CMOS FINFET, exploits set-partitioning principles and embedded per-survivor decision feedback to reduce implementation complexity and power consumption. The active area of the VD with 12 slices, each operating at one-eighth of the modulation rate, is 0.507 x 0.717mm2. Experimental results showing system performance are obtained by using a (215−1)-bit pseudo-random binary sequence. The impact of the synchronization length and survivor path memory length on the detector design and system performance are shown. A new pipelined reduced-state sequence detector algorithm is presented for high-speed implementations. A novel speculative symbol timing recovery scheme is proposed. New simulation results are obtained to compare the performance of the Reed–Solomon (RS)-encoded 4-PAM scheme with that of the concatenated RS four-dimensional (4-D) 5-PAM trelliscoded-modulation (TCM) scheme over an ideal band-limited additive-white-Gaussian-noise channel. Drawing on the results achieved for the VD, novel design techniques for a high-speed low complexity eight-state 4-D 5-PAM TCM decoder are proposed.
Index Terms — IEEE 802.3bj, IEEE 802.3bs, Viterbi detector, TCM decoder, 4-PAM, 5-PAM, four-dimensional, set partitioning, per-survivor decision feedback.
By: Hazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl
Published in: IEEE Transactions on Circuits and Systems. Part I: Regular Papers, volume 65, (no 10), pages 10.1109/TCSI.2018.2803735 in 2018
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