Equivalence Checking Using Cuts and Heaps

This paper presents a verification technique which is specifically targeted to formally comparing large combinational circuits with some structural similarities. The approach combines the application of BDDs with circuit graph hashing, automatic insertion of multiple cut frontiers, and a controlled elimination of false negative verification results caused by the cuts. Two ideas fundamentally distinguish the presented technique from previous approaches. First, originating from the cut frontiers, multiple BDD propagation is prioritized by size and discontinued once a given limit is exceeded. The resulting verification engine is robust and efficient for a wide varity of practical hardware designs ranging from identical circuits to design with very few similarities. Its effectiveness is demonstrated for a set of standard benchmark circuits and several large industrial designs.