We investigate the potential performance of PowerPC-based wide superscalar processors on a standard on-line transaction processing (OLTP) workload, using an instruction and data reference trace as input. We explore instruction-level parallelism as a function of the width of the processor, ranch prediction accuracy, size of cache memory, and policy for issuing instructions for execution performance factors are identified from the perspective of instruction retirement, highlighting the degradation contributed by different sources. The sensitivity to selected microarchitecture features is also studied. Simulation results validate common wisdom regarding the degrading effects of the memory subsystem, regardless of the width of the processor. The data also show that, for the workload and processor organitions considered, (1) dispatching more than eight instructions per cycle provides diminishing performance improvement; and (2) performance gains arising from out-of-order instruction issue increase with the processor width.
By: Jaime Moreno, Mayan Moudgill, John-David Wellman, Pradip Bose, Louise Trevillyan
Published in: RC20962 in 1997
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