Synchronous Interlocked Pipelined CMOS

In a circuit environment that is becoming increasingly sensitive to power dissipation and noise, and where locality principles are becoming paramount due to increasing wire delays and clock frequencies, the interlocking properties of asynchronous circuits provide a potential for reduced power and noise, and improved signal locality. However, since the vast majority of circuits and systems today are synchronous in nature it is desirable to achieve similar benefits in synchronous pipelines. So far it has not been understood how interlocking between stages can be achieved in a synchronous pipeline. This report presents a novel technique based on clock gating that achieves interlocking characteristics in synchronous pipelines similar to that of asynchronous pipelines. Furthermore, the technique provides improved storage capacity of synchronous pipelines and queues, allowing up to twice as many data items to be stored compared to traditional synchronous approaches. The presented technique is directly applicable to traditional synchronous pipelines and works equally well for two phase clocked pipelines based on transparent latches, as well as one phase clocked pipelines based on master-slave latches and flip-flops.