Dynamic Power Gating with Quality Guarantees

Power gating has emerged as a promising solution for reducing leakage energy consumption. However, power gating is usually driven by a predictive control and frequent mispredictions can counter-productively lead to a large increase in energy consumption. This energy vulnerability of the system could be exploited by malicious applications such as a power virus, or it may be exposed by regular applications containing repetitive mispredictions patterns. The possibility of these power overruns decreases the confidence in the overall design’s robustness, potentially leading to the power gating feature not being implemented in real processors, despite its large energy saving benefits in the common case.

In this work we document this vulnerability for a system implementing power gating of processor functional units. We propose to counteract this vulnerability by including a guard mechanism to ensure that the overall power gating control hardware is “safe” in the sense that power-overruns are prevented. Because power gating, with or without our guard mechanism, might be viewed as adding too much burden to processor verification, we demonstrate that functional correctness can be ensured for a system implementing power gating of processor functional units, with low supplementary verification effort.

By: Anita Lungu; Pradip Bose; Alper Buyuktosunoglu; Daniel J. Sorin

Published in: RC24948 in 2010


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