Low-Jitter 10-GHz Multiphase PLL in 90-nm CMOS

A 10-GHz multiphase PLL implemented in 90-nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 ps and 7 ps, respectively.

By: Marcel A. Kossel; Peter Buchmann; Christian Menolfi; Thomas Morf; Martin Schmatz; Thomas Toifl; Jonas Weiss

Published in: Electronics Letters, volume 41, (no 19), pages 1053-4 in 2005

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