Low-Jitter 10-GHz Multiphase PLL in 90-nm CMOS

A 10-GHz multiphase PLL implemented in 90-nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 ps and 7 ps, respectively.