The Influence of Transistor Properties on Performance Metrics and the Energy-Efficiency of Parallel Computations

To sustain the improvements in transistor integration density, performance, and energy per operation witnessed over the last five decades, semiconductor device engineers are investigating several device alternatives. They are however hard-pressed to relate observed transistor-level properties of potential CMOS replacements with the performance which might be achieved when these devices are used to construct complete integrated circuits such as microprocessors. This article addresses this challenge by developing a model linking device properties to algorithm properties (parallelism and total computational work) and system operation conditions (degree of voltage and frequency scaling). This framework is then used to provide insight into which aspects of transistor operation most influence execution time, average power dissipation, and overall energy usage of parallel algorithms executing in the presence of hardware concurrency. For the often-encountered challenge of jointly optimizing execution time and energy usage, the framework enables the expression of the appropriate form of joint energy-delay metric as a function of device properties. The presented analysis is supported by empirical characterizations of a dozen large digital circuit designs, and is further validated using performance and power measurements of a parallel algorithm executing on a state-of-the-art low-power multicore processor.

By: P. Stanley-Marbell

Published in: RZ3829 in 2012


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