Performance Driven Optimization of Network Length in Physical Placement

The locations of individual circuits in a placement have a significant impact on the wire length and therefore on the overall timing of designs. A novel technique that moves sets of circuits (gates) during or after timing driven placement to improve performance of designs is proposed. An efficient method to identify optimal set of circuit movements to reduce wire length, called strong motionsis presented. Experimental results with a min-cut placement tool indicate that the proposed approach of direct manipulation of circuit locations, improves the timing of partitions of a chip significantly.