In this paper, we present a high-speed AES IP-core, which runs at 780 MHz on a 0.13mm CMOS standard cell library, and which achieves 10 Gbps throughput in all encryption modes, including CBC mode. Although the CBC mode is the most widely used and important, achieving such high throughput was difficult because pipelining techniques cannot be applied. To reduce the propagation delays of the S-Box, the most critical function block, we developed a special circuit architecture that we call twisted-BDD, where the fanout of signals is distributed in the S-Box circuit. Our S-Box is 1.5 to 2 times faster than the conventional S-Box implementations. The T-Box algorithm, which merges the S-Box and another primitive function (MixColumns) into a single function, is also used for an additional speedup.
Also appeared in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 7, p. 686-91, July 2004
By: Sumio Morioka and Akashi Satoh
Published in: Proceedings of 2002 IEEE International Conference on Computer Design (ICCD): VLSI in Computers and ProcessorsLos Alamitos, CA, IEEE, p.98-103 in 2002
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