Integrated Analysis of Power and Performance for Pipelined Microprocessors

Copyright © (2004) by IEEE. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distrubuted for profit. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee.

Choosing the pipeline depth of a microprocessor is one of the most critical design decisions that an architect must make in the concept phase of a microprocessor design. To be successful in today’s cost/performance marketplace, modern CPU designs must effectively balance both performance and power dissipation. The choice of pipeline depth and target clock frequency has a critical impact on both of these important metrics. In this paper, we describe an optimization methodology based on both analytical models and detailed simulations for power and performance as a function of pipeline depth. Our results for a set of SPEC2000 applications show that when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of these energy models. Finally, we discuss the potential risks in design quality for overly aggressive or conservative choices of pipeline depth.

By: Pradip Bose, David M. Brooks, Philip G. Emma, Michael K. Gschwind, Vijayalakshmi Srinivasan, Philip N. Strenski, Victor Zyuban

Published in: IEEE Transactions on Computers, volume 53, (no 8), pages 1004-16 in 2004

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