Power-Aware Microarchitecture: Design and Modeling Challenges for the Next Generation Microprocesors

Copyright [©] (2001) by IEEE. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distrubuted for profit. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee.

Power dissipation limits have emerged as a major constraint in the design of microprocessors. This is true not only at the low end, where cost and battery life are the primary drivers, but also now at the midrange and high-end system (server) level. Thus, the ability to estimate power consumption at the high-level, during the early-stage definition and tradeoff studies is a key new methodology enhancement sought by design and performance architects. In this paper, we first review the fundamentals in terms of power estimation and power-performance tradeoffs at the microarchitecture level. We then discuss the opportunities of saving power that can be exposed via microarchitecture-level modeling. In particular, the potential savings that can be effected
through straightforward clock-gating techniques is cited as an example. We also describe home future ideas and trends in power-efficient processor design. Examples of how microarchitectural observations can be used towards power-saving circuit design optimizations are described. The design and modeling challenges highlighted in this paper are in the context o fwork in progress within IBM Research. This research is in support of future, high-end processor development within IBM.

By: David M.Brooks, Pradip Bose, Stanley E. Shuster,Hans Jacobson, Prabhakar N. Kudva, , Alper Buyuktosunoglu, John-David Wellman, Victor Zyuban, Manish Gupta and Peter W. Cook

Published in: IEEE Micro, volume 20, (no 6), pages 26-44 in 2001

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