This paper describes a semi-custom design methodology that was prototyped/demonstrated through the development of low-power high-performance DSP core. The developed methodology achieves significant speed improvement and reduction in power and area, compared with standard ASIC flow, without compromising its generality and high productivity. Because of the fast turn-around time from RTL description to post PD timing results, and stable convergence on timing the developed flow enables optimizations spanning multiple levels of the design hierarchy. Such optimizations proved much more effective than those that focus on any single phase of the design, which makes the described flow a compelling choice for the development of embedded processor cores.
By: V. Zyuban, S. Asaad, T. Fox, A. Haen, D. Littrell, J. Moreno
Published in: RC23027 in 2003
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