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This paper presents a multiphase PLL designed for a 10%10 Gb/s serial link bundle that is based on
a digital CDR receiver. The PLL was fabricated in a 90-nm SOI CMOS process and covers a frequency band of 9.6–12.8 GHz at a supply voltage of 1.7 V. Measurement results showed a peak-to-peak jitter of less than 0.12 UI and a power consumption efficiency of 1.5 mW/GHz per link. An
analytical derivation of the PLL’s tuning range and the dimensioning of the phase buffer’s shunt peaking coil to boost the bandwidth are also included in this paper.
By: Marcel A. Kossel; Thomas Morf; W. Baumberger; Alice Biber; Christian Menolfi; Thomas Toifl; Martin Schmatz
Published in: in 2005
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