The design of a compressed random access memory (C-RAM) is considered. Using a C-RAM at the lowest lever of a system's main memory hierarchy, cache lines are stored in a compressed format, and dynamically decompressed to handle cache misses at the next higher level of memory. The requirements that compression/decompression, address translation, and memory management be performed by hardware has implications for the directory structure and storage allocation designs used within the C-RAM. Various new approaches, presented here, are necessary in these areas in order to have methods that are amenable to hardware implementation. Furthermore, there are numerous design issues for the directory and storage management architectures. We consider a number of these issues, and evaluate various approaches using analytic methods and simulations
By: P. A. Franaszek, J. T. Robinson
Published in: RC21146 in 1998
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