Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors

        Scalable distributed shared-memory architectures rely on coherence controllers on each processing node to synthesize cache-coherent shared memory across the entire machine. The coherence controllers are responsible for executing coherence protocol handlers that may be hardwired in custom hardware, or programmed in a protocol processor within each coherence controller. Although custom hardware runs faster, a protocol processor allows the coherence protocol to be tailored to specific application needs and may shorten depvelopment time. Previous research show that the increase in application execution time due to protocol processors over custom hardware is minimal (<20%). However, with the advent of SMP processsing nodes and the availability of faster processors and networks, the trade-off between custom hardware and protocol processors needs to be reexamined. This paper studies the performance of custom-hardware and protocol-processor-based coherence controllers in SMP-node-based CC-NUMA systems on applications from the SPLASH-2 suite. Using realistic parameters and detailed models of existing state-of-the-art system components, it shows that the occupancy of coherence controllers can limit the performance of applications with high communication bandwidth requirements where the execution time using protocol processors can be twice as long as using custom hardware.

By: Maged M. Michael (Univ. of Rochester), Ashwini K. Nanda, Beng-Hong Lim and Michael L. Scott (Univ. of Rochester)

Published in: RC20675 in 1997

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