Alignment Technology for 3D Chip Stack

There are three types of three dimensional integration processes; the Chip-to-Chip process, Chip-to-Wafer process, and Wafer-to-Wafer process. In Japan, Chip-to-Chip processing is further advanced than the other two processes due to the package orientation. However, technology verification and new technology development in the Chip-to-Wafer and Wafer-to-Wafer processes have not advanced much due to certain issues (yield and costs) despite studies being conducted. A new low-cost, high-throughput Chip-to-Wafer 3D chip integration technique and a technique for high-precision auto alignment using soldering surface tension is developed. Soldering bumps for alignment is prepared and temporary alignment is made using soldering surface tension.

By: Katsuyuki Sakuma, Akihiro Horibe, and Shigenori Shimizu

Published in: RT5316 in 2010


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JP820080363_self alignment_research report_v2.pdf

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