A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 mu m CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.
By: Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Keven Stawiasz
Published in: RC23244 in 2004
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