Compared to conventional SRAM, embedded DRAM (eDRAM) offers power, bandwidth and density advantages for the design of large on-chip cache memories. However, eDRAM suffers from comparatively slower access times than conventional SRAM arrays.
Data prefetching offers an attractive solution for the latency problem of a large capacity eDRAM cache, by reducing the average access latency. Moreover, data prefetching allows better exploitation of the large eDRAM bandwidth by making efficient use of the wide data accesses.
In this work, we present an exploration of design trade-offs for the prefetch data cache in the Blue Gene/L supercomputer. We also compare our simulation results to measurement results on actual Blue Gene systems. These experiments provide a validation for our modeling environment. Actual execution time measurements also include any system effects not modeled in our performance analysis environment, and confirm the selection of simulation parameters included in the model.
By: Valentina Salapura, José R. Brunheroto, Fernando Redígolo, Alan Gara
Published in: RC24142 in 2006
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