Custom interconnect design complements automated route algorithms which do not guarantee the
generation of robust, legal routes for all signals in a ULSI design. The ability to forecast the effect
and degree of confidence that further intervention in an additional step will lead to similar improvement
would also be valuable information. This paper is the third in a series on physical design of on-chip
interconnections, and in this paper, we present analytical techniques to forecast when to continue and
when to stop the addition of custom interconnections in a design. The analytical techniques presented in this series of papers can also be incorporated in semi-custom and ASIC designs and may serve as tools to evaluate and improve various route algorithms.
By: Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David Conrady, Giovanni Fiorenza, I. Cevdet Noyan
Published in: RC22346 in 2002
LIMITED DISTRIBUTION NOTICE:
This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.
Questions about this service can be mailed to reports@us.ibm.com .