A Gate Leakage Reduction Technique for CMOS Diriver Circuits

We present a low-overhead circuit technique that mitigates gate leakage for sub-90nm technologies. In a circuit path, the effective driver strength is retained but divided into alwayson and gate-stress-relieved branches. During stand-by or after switching in the active mode, large devices are turned off or placed in a floating state that collapses over time, thus reducing the gate current. Total leakage reduction up to 54% can be observed for typical driver circuits.

By: J. B. Kuang; Hung C. Ngo; Kevin J. Nowka

Published in: RC23480 in 2005


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