Optimizing Flow Control for Buffered Switches

In our paper we address a problem often neglected in the presentation of credit flow control (FC) schemes for buffered switches, namely the issue of FC bandwidth and FC optimization, i.e. how many and which credits to return per packet cycle. Under the assumption of bursty traffic with uniform destinations we show via simulations that independent of switch size and without loss in performance the number of credits to be returned can be reduced to one. We further introduce the notion of credit contention and credit scheduling. We analyze four credit-scheduling strategies under varying system and buffer size. Our results demonstrate that with a proper credit scheduler in place contention resolution is resolved much faster than with conventional schemes. Our findings suggest that scheduling of credits is a means for the switch to determine its future arrivals during contention phases