Inaccuracies in Gate-Level Power Estimation

This paper studies the confidence with which power can be estimated at
various levels of design abstraction. We report the results of experiments
designed to identify and evaluate the sources of inaccuracies in
gate-level power estimation. In particular, we are interested in power
estimation during logic synthesis. Factors that may invalidate or
diminish the accuracy of power estimates include optimization,
technology mapping, transistor sizing, placement and wiring, and choice
of input stimuli.

By: D. Brand and C. Visweswariah

Published in: RC20520 in 1996


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