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High-level synthesis operates on internal models known as control/data flow graphs (CDFG)
and produces a register-transfer-level (RTL) model of the hardware implementation for a given
schedule. For high-level synthesis to be efficient it has to estimate the effect that a given algorithmic
decision (e.g., scheduling, allocation) will have on the final hardware implementation (after logic synthesis). The main problem in evaluating this effect is that the CDFGs are very distinct from the RTL/gate-level models used by logic synthesis. This makes it impossible to estimate hardware costs accurately. Moreover, the fact that high-level and logic synthesis operate on different internal models precludes on-the-fly interactions between these tools. This paper presents a solution to these problems consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL/gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.
By: Reinaldo Bergamaschi
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 21, (no 5), pages 582-96 in 2002
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