Performance analysis using standard benchmarks is necessary to evaluat e various tradeoffs during the design process. The increasing complexity of these benchmarks (e.g., from SPEC92 to SPEC95) combined with the relatively slow rate of detailed performance analysis has resulted in a widening gap between the size of the workload and the speed of analysis. This has necessitated the use of reduced traces that represent the original workload. Unfortunately, comprehensive method s of evaluating the representativeness of these reduced traces have been lacking. We present the first systematic method of evaluating such traces with respect to th e combined behavior of the processor and memory subsystems. Experimental results s how the usefulness of our metrics in the evaluation of any reduced trace and diagnos is of any detected deviations. We also present a method of synthesizing reduced tra ces which is more effective than the traditional sampling scheme for a class of benchmarks.
By: Vijay S. Iyengar and Louise H. Trevillyan
Published in: RC20610 in 1996
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