The SMART chip-- a joint development between the IBM Zurich Research Laboratory, the IBM Essonnes Device Development Laboratory and the IBM T.J. Watson Research Centre -- represents an SDH/SONET framer of the second generation. While first generation SDH/SONET framer ASICs are applicable to single SDH/SONET levels only (either STM-1/STS-3c or STM-4c), the scaleability concept of SMART allows to selectively map ATM cells either into STS-1, STM-1, STM-4 or STM-4c frames with a single chip. In addition to the enhanced transmission capabilities, SMART provides on-chip support for exploiting the add-drop, digital cross-connect and automatic protection functions of SDH/SONET. SMART is the first commercially available ASIC applicable not only in path termination, but also in multiplex section equipment. This report describes the functional requirement specifications of SMART.
By: A. Herkersdorf
Published in: RZ2930 in 1998
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