An innovative low-power high-performance programmable signal processor for digital communications

We describe an innovative low-power high-performance programmable signal processor (DSP) for digital communications. The architecture of this processor is characterized by its explicit design for low-power implementations, its innovative ability to jointly exploit instruction-level parallelism (ILP) and data-level parallelism (SIMD) to achieve high-performance, its suitability as target for an optimizing high-level language compiler, and its explicit replacement of hardware resources by compile-time practices. We describe the methodology used in the development of the processor, highlighting the techniques deployed to enable architecture/compiler/implementation co-development, and the approach used for power-performance evaluation and trade-off analysis. We summarize the salientfeaturesofthe architecture,provide a brief descriptionofthe hardware organization,and discuss the compiler techniques used to exercise these features. We also summarize the simulation environment and associated software development tools. Coding examples from two representative kernels in the digital communications domain are also provided. The resulting design methodology, architecture and compiler represent an advance of the state-of-the-art in the area of low-power domain specific microprocessors.