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Eight Synergistic Processor Units enable the Cell Broadband Engine’s breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism.
By: Michael Gschwind; H Peter Hofstee; Brian Flachs; Marty Hopkins; Yukio Watanabe; Takeshi Yamazaki
Published in: IEEE Micro, volume 26, (no 2), pages 10-24 in 2006
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