Synergistic Processing in Cell's Multicore Architecture

Copyright © (2006) by IEEE. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distrubuted for profit. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee.

Eight Synergistic Processor Units enable the Cell Broadband Engine’s breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism.

By: Michael Gschwind; H Peter Hofstee; Brian Flachs; Marty Hopkins; Yukio Watanabe; Takeshi Yamazaki

Published in: IEEE Micro, volume 26, (no 2), pages 10-24 in 2006


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