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Leading-edge systems-on-chip (SoC) being designed today could reach 20 Million gates and 0.5 to 1 GHz operating frequency. In order to implement such systems, designers are increasingly relying on reuse of intellectual property (IP) blocks. Since IP blocks are predesigned and preverified, the designer can concen-trate on the complete system without having to worry about the correctness or performance of the individ-ual components. That is the goal, in theory. In practice, assembling an SoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discusses the main challenges in SoC designs using IP blocks and elaborates on the methodology and tools being researched at IBM for addressing the problem. It explains IBM’s SoC architecture and gives algorithmic details on the high-level tools being developed for SoC design.
By: Reinaldo A. Bergamaschi, Subhrajit Bhattacharya,Ronaldo Wagner(IBM EDA Lab Fishkill, NY ) Colleen Fellenz (IBM EDA Lab Fishkill,NY) William R. Lee (Cisco Systems Raleigh,NC) Foster White (Nortel Networks Raleigh NC) Michael Muhlada (Cisco Systems Raleigh,NC) Jean-Marc Daveau (ST Micrelectronics,Grenoble France)
Published in: IEEE Design and Test of Computers, volume 18, (no 5), pages 32-45 in 2001
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