Quality Improvement Methods for System-Level Stimuli Generation

Functional verification is known to be a major part of the hardware design effort. System verification is aimed at validating the integration of several previously verified components. As such, it deals with complex designs, and invariably suffers from tight schedules and scarce resources. We present a set of methods, collectively known as testing knowledge, aimed at increasing the quality of automatically generated system-level test-cases. These methods are based on the commonality of some basic architectural concepts. Testing knowledge reduces the time and effort required to achieve high coverage of the verified design. Towards the end of the paper, we compare the coverage achieved with and without the usage of testing knowledge, and describe related hardware bugs.

By: Roy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh

Published in: H-0215 in 2003


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