A new architecture for SDH/SONET components and entire framers is introduced. The architecture allows building highly configurable SDH/SONET components suitable as system-on-chip cores as well as single-chip data aggregation framers with add/drop, cross-connect, and multiplexing functionality for a large number of line ports with different data rates.
By: Rolf Clauberg and Peter Buchmann
Published in: RZ3426 in 2002
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