Floating Body Effects in Pass-Transistor Based CMOS Circuits with Partially-Depleted SOI Devices

        This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various pass-transistor based CMOS circuits. Pass-transistor based designs including pass-gate based latches, muliplexers, series pass-gates, multiplexed pass-gate latches, and pseudo 2-phase dynamic logic are examined. The parasitic bipolar effect resulting from the floating body configuration in shown to degrade the circuit noise margin and stability in general. For the cases of wide multiplexers and pseudo 2-phase dynamic logic, the parasitic bipolar effect is shown to potentially lead to logic state errors.

By: J. Ji, C.T. Chuang, P. F. Lu, L. F. Wagner (IBM Semiconductor Res. & Devlopment Ctr., Hopwell Jnct.), C. M. Hsieh (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.), L. Hsu (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.), J. B. Kuang (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.), M. M. Pelella (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.), S. Chu (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.) and C. J. Anderson

Published in: RC20393 in 1996

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