Circuit Implications of Gate Oxide Breakdown

A model for the oxide breakdown (BD) current-voltage (IV) characteristics has been experimentally verified on CMOS inverters. The implications of oxide BD on the performance of various CMOS circuit elements are discussed. Examples are shown of cell stability and bitline differentials in static memory (SRAM), signal timing,
and inverter chains.

By: James H. Stathis, Rosana Rodriguez, Barry Paul Linder

Published in: Microelectronics Reliability, volume 43, (no 8), pages 1193-7 in 2003

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