Graphene Field-Effect Transistors with Self-Aligned Gates

We present a new device fabrication process that produces graphene-based field-effect transistors with self-aligned gates. This process utilizes the inherent nucleation inhibition of atomic-layer-deposited films with the graphene surface to achieve electrical isolation of the gate electrode from the source/drain electrodes while maintaining electrical access to the graphene channel. Self-alignment produces access lengths of 15 - 20 nm, which allows for improved device stability, performance, and a minimal normalized contact resistance of 540 Ω μm.

By: Damon B. Farmer; Yu-Ming Lin; Phaedon Avouris

Published in: RC24987 in 2010


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