CMOS scaling with SiO2 or oxynitride gate dielectrics for advanced high-performance logic and memory has reached a point where one or several oxide breakdown (BD) events are expected over the life of a chip. [1,2] Previous oxide reliability projections were based on the assumption that a single breakdown (soft or hard) on a chip would cause circuit failure, which is no longer believed to be correct. For accurate reliability projections it is necessary to better understand the nature of the BD event and the effect of BD on circuits.
By: James H. Stathis
Published in: RC23569 in 2005
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