A small change in the input to logic synthesis may cause a large change in the
output implementation. This is undesirable if the designer has some investment
in the old implementation and does not want it perturbed more than necessary.
We describe a method that solves this problem by reusing gates from the old
implementation, and restricting synthesis to modified portions only.
By: Daniel Brand, Anthony D. Drumm, Sandip Kundu and Prakash Narain
Published in: RC20352 in 1996
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