Wirelength distributions for signals associated with functional logic circuitry and synchronization circuitry in ultralarge-scale integrated circuit designs

The synchronization of functional logic signals in computer hardware components is required for successful design and implementation of high-performance hardware. The goal of this paper is to obtain methods to quantify the requirements of the two groups of signals. Most of the work concerning Rent’s Rule prior to the present paper has been based on a 1971 interpretation of two unpublished memoranda written in 1960 by E. F. Rent at IBM, even though today’s computer components require, in addition to
their logic function, a complex synchronization network that synchronizes the operation of functional logic at today’s multi-GHz frequencies. In this paper, we will refer to the type of signals and circuitry that are associated with logic function with the term function type and will use the term synchronization type to refer to the remaining circuits and signals; most of the remaining signals are associated with a clocking network superimposed on the functional logic, and the rest perform other non-functional tasks
such as clock control and scan. Prior work does not distinguish among signals and circuitry according to these two types: function type and synchronization type. However, because of the increasingly complex design and implementation of synchronization circuitry since 1960-1971 for high-performance chips, an understanding of the separate requirements of both types is needed. To address this point, we have obtained copies of Rent’s two original memos in which Rent describes functional logic of two 1960 computers and describes a method to assess connections and circuits associated with functional logic. In this paper, we will: (1) discuss the two types; (2) apply an historically-equivalent interpretation of Rent’s Rule to circuitry with function type in actual ultralarge scale integrated (ULSI) circuit designs; (3) present a new empirical model for wire-length distributions for circuitry with synchronization type; and (4) compare these models with wire-length distributions for signals of both types for 100 POWER4 control logic designs. We will show that these methods provide greatly improved qualitative agreement with actual wire-length distributions compared with prior methods.