Advanced Undergraduate Project: Effects on Device Scaling on CMOS Imager Performance

The goal of this study is to examine the effects of device scaling on CMOS imager performance. In order to do this, an array of twenty-four pixels was constructed, arranged in a 3 by 8 matrix. The right half of the pixels utilize photogates to capture incoming light, while the left half employs photodiodes for the same purpose. Each pixel is 7 microns wide by 7 microns long and has a fill factor (percentage of light-sensitive area to the total pixel area) of approximately 33%. These circuits were fabricated with an effective channel length of 0.25 um, a 40 nm thick oxide layer, and a 1.8V power supply technology. In this study, particular emphasis is given to potential problems that imagers may face when using such small technologies. The work for this paper was done at the IBM T.J. Watson Research Center in Yorktown Heights, New York, and is documented in conjunction with the paper, CMOS Active Pixel Image Sensors Fabricated Using a 1.8V, 0.25 um CMOS Technology, to be presented at the 1996 International Electron Devices Meeting.