As technology scales the power supplyVdd is being lowered in order to lower operating power and to meet device reliability requirements. Because of the increase in noise and leakage, however, the threshold voltage VT is not being lowered at the same rate as Vdd. This results in an increase in the sensitivity of circuit delay to power supply noise, and underscores the need to perform detailed analysis of the on chip power distribution for noise, robustness and reliability. A common technique applied in the analysis of on-chip power grids is to separate the linear and non-linear components of the problem and treat them separately (see for example [2], [4] and [7]). With the increasing sensitivity of delay to power grid noise, this artificial separation can lead to subtle errors, especially for otherwise marginal designs.
By: Sani R. Nassif, Haihua Su
Published in: RC22400 in 2002
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