Technology scaling and the push for ever increased performance has resulted in the rapid increase of integrated circuit power dissipation. We are already in the era of the 100 Watt IC [1]. This necessitates the detailed modeling and analysis of the on-chip power distribution for robustness and reliability [2, 3, 4]. An important component of this model is the decoupling capacitance of the design which includes dedicated decoupling capacitors as well as the capacitance of non-switching circuits. This paper describes a technique for modeling the decoupling capacitance of circuits. An exact simulation-based method is outlined, and fast but accurate analytical models are proposed.
By: Sani R. Nassif; Kanak Agarwal; Emrah Acar
Published in: RC23670 in 2005
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