An Input Queueing Implementation for Low-Latency Speculative Optical Switches

Switching fabrics using speculative scheduling are emerging as a promising way to tackle the latency problem in optical computer interconnects. This paper presents an input queueing architecture and hardware to process regular request/grant and speculative arbitration in an integrated fashion. The OSMOSIS research demonstrator co-built by Corning and IBM is a 64 port optoelectronic switch with a Broadcast & Select optical switching fabric and central arbiter, running at 40 Gbps per port. The demonstrator is built using Xilinx Virtex II Pro and Altera Stratix FPGAs. A speculative protocol bypasses the latency of the control channel by transmitting a cell from input port adapters to the optical switching fabric, ahead of the corresponding grant from the central scheduler. This paper discusses various input queueing architecture alternatives. FPGA sizing and speed results from synthesis of the selected queueing architecture to Altera Stratix are presented. A novel dual-tree round-robin queue scheduler hardware structure is proposed and evaluated to overcome the poor mapping properties of priorityarbiter schedulers to FPGAs. The dual-tree structure outperforms the conventional priority-arbiter structure by a factor of two when integrated in a queueing architecture.

A condensed version of this Research Report was published the Proceedings of tThe 2007 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA 2007), Las Vegas, USA.

By: Raj B. Krishnamurthy; Peter Mueller

Published in: RZ3665 in 2006


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