SRAM behavior for FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD/SOI) technology. Unique FinFET circuit behavior in SRAM applications, resulting from the near-ideal device characteristics, is demonstrated by full cell cross section simulation for the first time, and shows high performance and low active and standby power. SRAM stability is in detail analyzed as compared to PD/SOI .
By: Rajiv V. Joshi, Richard Q. Williams, Ed Nowak, Keunwoo Kim, Jochen Beintner, T. Ludwig, I. Aller, C. Chuang
Published in: RC23171 in 2004
LIMITED DISTRIBUTION NOTICE:
This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.
Questions about this service can be mailed to reports@us.ibm.com .