FinFET SRAM for High-Performance Low-Power Applications

SRAM behavior for FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD/SOI) technology. Unique FinFET circuit behavior in SRAM applications, resulting from the near-ideal device characteristics, is demonstrated by full cell cross section simulation for the first time, and shows high performance and low active and standby power. SRAM stability is in detail analyzed as compared to PD/SOI .

By: Rajiv V. Joshi, Richard Q. Williams, Ed Nowak, Keunwoo Kim, Jochen Beintner, T. Ludwig, I. Aller, C. Chuang

Published in: RC23171 in 2004


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