In this paper, we demonstrate InGaAs FinFETs 3D sequentially (3DS) integrated on top of a fully-depleted silicon-on-insulator CMOS. Top layer III-V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. The low thermal budget of the top layer process caused no performance degradation of the lower level FETs. Record ION of 200 µA/µm (at IOFF = 100 nA/µm and VDD = 0.5 V) for 3DS integrated III-V FETs on silicon is demonstrated, with a 50% reduction of RON compared to previous work. The achieved improved performance can be attributed to the introduction of doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.
Keywords: 3DS, III-V, FinFETs, sequential integration, wafer bonding, monolithic integration
By: C. Convertino, C. B. Zota, D. Caimi, M. Sousa and L. Czornomaz
Published in: 48th European Solid-State Device Research Conference (ESSDERC), IEEE, p.10.1109/ESSDERC.2018.8486862 in 2018
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