We present dynamic circuit techniques for conditional dynamic node keeping, charge sharing prevention, and clock load reduction in symmetrical and asymmetrical double-gate devices. By utilizing the unique technology feature, performance benefit, noise immunity, area and power efficiency can be achieved in circuits when front and back gate are independently biased in a judicious manner.
By: J. B. Kuang; K. Kim; C. T. Chuang; H. C. Ngo; K. J. Nowka
Published in: RC23716 in 2005
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