Chip-level power dissipation limits constitute a fundamental design constraint in future highperformance
microprocessors. Recently, there has been an industry-wide trend of shifting towards lower frequencies and multiple cores to meet next generation performance targets at affordable power. Nonetheless, even with reduced per-core frequency, the chip-level performance targets for such a multi-core processor are aggressive, and meeting the power budget at those performance levels continues to present a major design challenge. On-chip, dynamic power management is therefore a design feature that is likely to be an integral part of the overall architecture. Initial analysis has shown that clock-gating alone is not enough to meet the chip-level power budget for a high-end multi-core design. Both average and maximum power must be managed to remain within acceptable limits, dictated by power-related maintenance cost budgets and cooling/packaging solution cost limits.
By: Canturk Isci; Alper Buyuktosunoglu; Pradip Bose; Chen-Yong Cher
Published in: RC23890 in 2006
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